Top Related Projects
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
A FPGA friendly 32 bit RISC-V CPU implementation
Rocket Chip Generator
Quick Overview
The pulp-platform/pulpino repository is a RISC-V-based microcontroller system-on-chip (SoC) designed for low-power embedded applications. It is an open-source project that provides a complete hardware and software stack, including a processor core, peripherals, and a software development environment.
Pros
- Low-Power Consumption: The Pulpino SoC is designed with a focus on energy efficiency, making it suitable for battery-powered and IoT devices.
- Modular and Customizable: The Pulpino architecture is highly modular, allowing users to customize the SoC by adding or removing components as needed.
- Open-Source: The Pulpino project is open-source, providing users with the flexibility to modify and extend the design to suit their specific requirements.
- RISC-V Instruction Set: The Pulpino SoC is based on the RISC-V instruction set, which is an open and royalty-free architecture, enabling a wide range of applications and ecosystem support.
Cons
- Limited Documentation: The project's documentation, while available, could be more comprehensive and user-friendly, especially for newcomers to the RISC-V ecosystem.
- Ongoing Development: As an active research project, the Pulpino SoC may undergo frequent changes and updates, which could impact the stability and compatibility of the system.
- Niche Market: The Pulpino SoC is primarily targeted at the low-power embedded market, which may limit its broader adoption and community support compared to more mainstream microcontroller platforms.
- Lack of Commercial Support: As an open-source project, the Pulpino SoC does not have the same level of commercial support and ecosystem as proprietary microcontroller solutions.
Getting Started
To get started with the Pulpino SoC, you can follow the instructions provided in the project's README.md file. Here's a brief overview:
- Clone the Pulpino repository:
git clone https://github.com/pulp-platform/pulpino.git
- Install the required dependencies, including the RISC-V toolchain and Verilator (a hardware simulation tool):
cd pulpino
./install.sh
- Build the Pulpino SoC and run the simulation:
make clean
make all
make run
This will compile the Pulpino hardware and software, and start the simulation. You can then interact with the simulated Pulpino SoC using the provided software tools and examples.
Competitor Comparisons
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Pros of Ibex
- More actively maintained with frequent updates and contributions
- Broader industry support and adoption, including use in OpenTitan project
- Extensive documentation and user guides available
Cons of Ibex
- Less focus on ultra-low power applications compared to PULPino
- May have a steeper learning curve for beginners due to its more complex architecture
Code Comparison
PULPino (RISC-V core):
always_comb
begin
alu_operand_a_ex_o = alu_operand_a;
alu_operand_b_ex_o = alu_operand_b;
alu_operand_c_ex_o = alu_operand_c;
bmask_a_ex_o = bmask_a_id;
bmask_b_ex_o = bmask_b_id;
Ibex (RISC-V core):
always_comb begin
alu_operator_o = ALU_SLTU;
alu_op_a_mux_sel_o = OP_A_IMM;
alu_op_b_mux_sel_o = OP_B_IMM;
imm_b_mux_sel_o = IMM_B_I;
regfile_we = 1'b0;
Both repositories implement RISC-V cores, but Ibex offers a more modern and widely supported implementation, while PULPino focuses on ultra-low power applications. The code snippets show similarities in their ALU implementations, with slight differences in naming conventions and signal organization.
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Pros of cv32e40p
- More active development and community support
- Enhanced performance and power efficiency
- Broader range of supported extensions and custom instructions
Cons of cv32e40p
- Higher complexity and learning curve
- Less documentation for beginners compared to PULPino
Code Comparison
PULPino:
module riscv_core
#(
parameter N_EXT_PERF_COUNTERS = 0,
parameter INSTR_RDATA_WIDTH = 32,
parameter PULP_SECURE = 0,
parameter N_PMP_ENTRIES = 16,
parameter USE_PMP = 1,
parameter PULP_CLUSTER = 0,
parameter FPU = 0,
parameter SHARED_FP = 0,
parameter SHARED_FP_DIVSQRT = 2
)
cv32e40p:
module cv32e40p_core import cv32e40p_pkg::*;
#(
parameter LIB = 0,
parameter rv32_e RV32 = RV32I,
parameter b_ext_e B_EXT = B_NONE,
parameter m_ext_e M_EXT = M,
parameter bit X_EXT = 0,
parameter int unsigned X_NUM_RS = 2,
parameter int unsigned X_ID_WIDTH = 4,
parameter int unsigned X_MEM_WIDTH = 32,
parameter int unsigned X_RFR_WIDTH = 32,
parameter int unsigned X_RFW_WIDTH = 32,
parameter logic [31:0] X_MISA = 32'h00000000,
parameter int unsigned NUM_MHPMCOUNTERS = 1
)
Both repositories provide RISC-V core implementations, but cv32e40p offers more advanced features and customization options, while PULPino focuses on simplicity and ease of use for beginners.
A FPGA friendly 32 bit RISC-V CPU implementation
Pros of VexRiscv
- Written in SpinalHDL, allowing for more flexible and modular design
- Supports a wider range of RISC-V extensions and custom instructions
- Offers better performance and smaller area footprint in many configurations
Cons of VexRiscv
- Less mature ecosystem and documentation compared to PULPino
- Steeper learning curve due to SpinalHDL usage instead of traditional HDLs
- Fewer pre-built SoC examples and peripherals available out-of-the-box
Code Comparison
PULPino (VHDL):
entity riscv_core is
port (
clk_i : in std_logic;
rst_ni : in std_logic;
instr_req_o : out std_logic;
instr_gnt_i : in std_logic;
instr_rvalid_i : in std_logic;
instr_addr_o : out std_logic_vector(31 downto 0);
VexRiscv (SpinalHDL):
class VexRiscv(config : VexRiscvConfig) extends Component {
val io = new Bundle {
val iBus = master(IBusSimplified(config.iBusConfig))
val dBus = master(DBusSimplified(config.dBusConfig))
val interrupt = in Bool()
val debug = config.withDebug generate new Area {
The code snippets show the different languages and approaches used in each project, with PULPino using traditional VHDL and VexRiscv leveraging SpinalHDL's more concise and flexible syntax.
Rocket Chip Generator
Pros of Rocket Chip
- More comprehensive and feature-rich RISC-V implementation
- Supports a wider range of configurations and customizations
- Backed by a larger community and industry support
Cons of Rocket Chip
- Higher complexity and steeper learning curve
- Requires more resources to implement and simulate
- Less suitable for small-scale or low-power applications
Code Comparison
PULPino (simplified RISC-V core):
module riscv_core
(
// Clock and Reset
input logic clk_i,
input logic rst_ni,
// ...
);
// Core implementation
endmodule
Rocket Chip (more complex RISC-V implementation):
class Rocket(implicit p: Parameters) extends CoreModule()(p)
with HasFpuParameters
with HasCoreParameters
with HasL1ICacheParameters
with HasL1DCacheParameters {
// Complex core implementation
}
PULPino focuses on a simpler, more accessible RISC-V implementation suitable for IoT and embedded systems. It offers a straightforward Verilog codebase and targets low-power applications.
Rocket Chip provides a highly configurable and extensible RISC-V implementation using Chisel. It's designed for scalability and supports a wide range of use cases, from embedded systems to high-performance computing.
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Introduction
PULPino is an open-source single-core microcontroller system, based on 32-bit RISC-V cores developed at ETH Zurich. PULPino is configurable to use either the RISCY or the zero-riscy core.
RISCY is an in-order, single-issue core with 4 pipeline stages and it has an IPC close to 1, full support for the base integer instruction set (RV32I), compressed instructions (RV32C) and multiplication instruction set extension (RV32M). It can be configured to have single-precision floating-point instruction set extension (RV32F). It implements several ISA extensions such as: hardware loops, post-incrementing load and store instructions, bit-manipulation instructions, MAC operations, support fixed-point operations, packed-SIMD instructions and the dot product. It has been designed to increase the energy efficiency of in ultra-low-power signal processing applications. RISCY implementes a subset of the 1.9 privileged specification. Further informations can be found in http://ieeexplore.ieee.org/abstract/document/7864441/.
zero-riscy is an in-order, single-issue core with 2 pipeline stages and it has full support for the base integer instruction set (RV32I) and compressed instructions (RV32C). It can be configured to have multiplication instruction set extension (RV32M) and the reduced number of registers extension (RV32E). It has been designed to target ultra-low-power and ultra-low-area constraints. zero-riscy implementes a subset of the 1.9 privileged specification.
When the core is idle, the platform can be put into a low power mode, where only a simple event unit is active and everything else is clock-gated and consumes minimal power (leakage). A specialized event unit wakes up the core in case an event/interrupt arrives.
For communication with the outside world, PULPino contains a broad set of peripherals, including I2S, I2C, SPI and UART. The platform internal devices can be accessed from outside via JTAG and SPI which allows pre-loading RAMs with executable code. In standalone mode, the platform boots from an internal boot ROM and loads its program from an external SPI flash.
The PULPino platform is available for RTL simulation as well FPGA. PULPino has been taped-out as an ASIC in UMC 65nm in January 2016. It has full debug support on all targets. In addition we support extended profiling with source code annotated execution times through KCacheGrind in RTL simulations.
Requirements
PULPino has the following requirements
- ModelSim in reasonably recent version (we tested it with versions >= 10.2c)
- CMake >= 2.8.0, versions greater than 3.1.0 recommended due to support for ninja
- riscv-toolchain, specifically you need riscv32-unknown-elf-gcc compiler and friends. There are two choices for this toolchain: Either using the official RISC-V toolchain supported by Berkeley or the custom RISC-V toolchain from ETH. The ETH versions supports all the ISA extensions that were incorporated into the RI5CY core as well as the reduced base instruction set for zero-riscy. Please make sure you are using the newlib version of the toolchain.
- python2 >= 2.6
- verilator 3.884 only necessary if you want to use Verilator to evaluate PULPino.
ISA Support
PULPino can run either with RISCY or zero-riscy.
The software included in this repository is compatible with both the cores
and automatically targets the correct ISA based on the flags used.
The simulator (modelsim) must be explicitely told which edition you want to build.
Use the environment variable USE_ZERO_RISCY and set it to either 1 for zero-riscy or
0 for RISCY.
Version Control
PULPino uses multiple git subrepositories
To clone those subrepositores and update them, use
./update-ips.py
This script will read the ips_lists.txt file and update to the versions
specified in there. You can choose specific commits, tags or branches.
Documentation
There is a preliminary datasheet available that includes a block diagram and a memory map of PULPino. See docs/datasheet/ in this repository.
It is written in LaTeX and there is no pdf included in the repository. Simply type
make all
inside the folder to generate the pdf. Note that you need a working version of latex for this step.
Running simulations
The software is built using CMake. Create a build folder somewhere, e.g. in the sw folder
mkdir build
Copy the cmake-configure.{*}.gcc.sh bash script to the build folder. This script can be found in the sw subfolder of the git repository.
Modify the cmake-configure script to your needs and execute it inside the build folder. This will setup everything to perform simulations using ModelSim.
Four cmake-configure bash scripts have been already configured:
- cmake_configure.riscv.gcc.sh
It automatically selects the RISCY cores and compiles SW with all the PULP-extensions and the RV32IM support. The GCC ETH compiler is needed and the GCC march flag set to "IMXpulpv2".
- cmake_configure.riscvfloat.gcc.sh
It automatically selects the RISCY cores and compiles SW with all the PULP-extensions and the RV32IMF support. The GCC ETH compiler is needed and he GCC march flag set to "IMFXpulpv2".
- cmake_configure.zeroriscy.gcc.sh
It automatically selects the zero-riscy cores and compiles SW with the RV32IM support (march flag set to RV32IM).
- cmake_configure.microriscy.gcc.sh
It automatically selects the zero-riscy cores and compiles SW with the RV32E support. The slim GCC ETH compiler is needed and he GCC march flag set to "RV32I" and the "-m16r" is passed to the compiler to use only the RV32E ISA support.
Activate the RVC flag in the cmake file if compressed instructions are desired.
Inside the build folder, execute
make vcompile
to compile the RTL libraries using ModelSim.
To run a simulation in the modelsim GUI use
make helloworld.vsim
To run simulations in the modelsim console use
make helloworld.vsimc
This will output a summary at the end of the simulation. This is intended for batch processing of a large number of tests.
Replace helloworld with the test/application you want to run.
Using ninja instead of make
You can use ninja instead make to build software for PULPino, just replace all occurrences of make with ninja. The same targets are supported on both make and ninja.
Interactive debug
To interactively debug software via gdb, you need the jtag bridge as well as a
working version of gdb for the ISA you want to debug. The debug bridge depends
on the jtag_dpi package that emulates a JTAG port and provides a TCP socket
to which the jtag bridge can connect to.
Utilities
We additionally provide some utilitiy targets that are supposed to make development for PULPino easier.
For disassembling a program call
make helloworld.read
To regenerate the bootcode and copy it to the rtl folder use
make boot_code.install
FPGA
PULPino can be synthesized and run on a ZedBoard.
Take a look at the fpga subfolder for more information.
Creating a tarball of the PULPino sources
If for some reason you don't want to use the git sub-repository approach, you
can create a tarball of the whole design by executing ./create-tarball.py.
This will download the latest PULPino sources, including all IPS, remove the
git internal folders and create a tar gz.
Arduino compatible libraries
Most of official Arduino libraries are supported by PULPino software, they can be compiled, simulated and uploded the same way as traditional software programs using the available PULPino utilities. You only need to include main.cpp at the beginning of the program:
#include "main.cpp"
Take a look at the sw/libs/Arduino_libs subfolder for more information about
the status of the currently supported libraries.
Top Related Projects
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
A FPGA friendly 32 bit RISC-V CPU implementation
Rocket Chip Generator
Convert designs to code with AI
Introducing Visual Copilot: A new AI model to turn Figma designs to high quality code using your components.
Try Visual Copilot